ISimの使い方

module t_FAFS;

	// Inputs
	reg SW1;
	reg SW2;
	reg SW3;
	reg SW4;

	// Outputs
	wire LD1;
	wire LD2;

	// Instantiate the Unit Under Test (UUT)
	FAFS uut (
		.SW1(SW1), 
		.SW2(SW2), 
		.SW3(SW3), 
		.SW4(SW4), 
		.LD1(LD1), 
		.LD2(LD2)
	);

	integer i,j,k;

	initial begin
		// Initialize Inputs
		SW1 = 0;
		SW2 = 0;
		SW3 = 0;
		SW4 = 0;

		// Wait 100 ns for global reset to finish
		#100;

		// Add stimulus here
		for(i=0; i<2; i=i+1)
		begin
			for(j=0; j<2; j=j+1)
			begin
				for(k=0; k<2; k=k+1)
				begin
					#10 SW1 = SW1 + 1'b1;
				end
				SW2 = SW2 + 1'b1;
			end
			SW3 = SW3 + 1'b1;
		end
	end
      
endmodule